This invention relates to integrated circuits and, more particularly, to circuitry that implements multi-mode redundancy and arithmetic functions in integrated circuits.
Integrated circuits are subject to a phenomenon known as single event upset (SEU). A single event upset is a change of state caused by ions or electro-magnetic radiation. Cosmic rays or radioactive impurities embedded in integrated circuits and their packages may be responsible for generating such ions or electro-magnetic radiation. When ions or electro-magnetic radiation strike the silicon substrate on which the integrated circuit is implemented, the state of a node may change. For example, a single event upset may cause a logic “1” to change to a logic “0”.
Upset events in sequential elements (e.g., memory elements, latches, or registers) can have serious repercussions. Users who are concerned with detecting and correcting errors in a design or a portion of a design that is implemented in an integrated circuit often create multiple copies of that design or that portion of the design. A majority vote of the outputs produced by the different design copies may enable the detection of an upset event and indicate the location of the corrupted design copy. The technique of using multiple copies of a same design together with a majority vote is sometimes also referred to as multi-mode redundancy.
However, multi-mode redundancy requires multiple times the circuit area of a single design implementation plus the cost and delay associated with resources required for the implementation of the majority voting circuitry.
It would therefore be desirable to reduce the cost and delay associated with implementing multi-mode redundancy on an integrated circuit.